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| Product
Name:
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Specifications:
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| Power consumption
| +5V Operating (A/D
converting to FIFO) |
0.8A typical, 1.0A max |
|
Analog Input Section
| A/D converter type |
7800 |
| Resolution |
12 bits |
| Number of channels |
8 differential or 16
single-ended, software selectable |
|
Input Ranges
|
PCI-DAS1000 |
±10V, ±5V, ±2.5V,
±1.25V, 0 to 10V, 0 to 5V, 0 to 2.5V, 0 to 1.25V fully programmable |
| PCI-DAS1001 |
±10V, ±1V, ±0.1V,
±0.01V, 0 to 10V, 0 to 1V, 0 to 0.1V, 0 to 0.01V fully programmabled |
| Polarity |
Unipolar/Bipolar,
software selectable |
| A/D pacing |
Programmable: internal
counter or external source (A/D External Pacer, positive or negative
edge selectable by software) or software polled |
|
Burst Mode
| PCI-DAS1000 |
Software selectable
option, rate = 4 µs |
|
PCI-DAS1001 |
Software selectable
option, rate = 6.67 µs |
| A/D Trigger sources |
External digital (A/D
External Trigger) |
|
A/D Triggering Modes
| Digital |
Software enabled,
rising edge, hardware trigger |
| Pre-trigger: |
Unlimited pre- and
post-trigger samples. Total # of samples must be > 512. |
| Data transfer |
From 1024 sample FIFO
via REPINSW, interrupt or software polled |
| A/D conversion time |
3µs |
|
Throughput
| PCI-DAS1001 |
150 kHz |
| PCI-DAS1000 |
250 kHz |
| Relative Accuracy |
±1.5LSB |
| Differential Linearity
error |
±0.75 LSB |
| Integral Linearity
error |
±1.5 LSB |
| Gain
Error (relative to calibration reference) |
| 0.01V Range
|
± 0.4% of reading Max
|
| All other Ranges
|
0.02% of reading Max
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| No missing codes
guaranteed |
12 bits |
| Calibration |
Auto-calibration,
calibration factors for each range stored on board |
| Gain drift (A/D specs)
|
±6ppm/°C |
| Zero drift (A/D specs) |
±1ppm/°C |
| Common Mode Range |
±10V |
| CMRR @ 60Hz |
70dB |
| Input leakage current
|
200nA |
| Input impedance |
10Meg Ohms Min |
|
Absolute maximum input voltage
| PCI-DAS1001 |
±35V |
| PCI-DAS1000 |
Channels 1-15:
-40V to +55V power on or off
Channel 0: ±15V |
|
Noise Distribution (Rate = 1-250KHz, Average % ±2
bins, Average % ±1 bin, Average # bins)
|
PCI-DAS1000 |
| All Bipolar ranges
|
100% / 99.5% / 4 bins |
| All Unipolar
|
100% / 99% / 5 bins |
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|
PCI-DAS1001 |
| 10V Ranges |
3 bins (100%) |
| 1V Ranges
|
4 bins (100%) |
| 0.1V Ranges |
10 bins (100%) |
| Bipolar 0.01V
Range |
20 bins (100%) |
| Unipolar 0.01V
Range |
32 bins (100%) |
|
|
A/D Triggering Modes
|
Digital |
Analog |
Pre-trigger |
Software-configurable for Edge (triggered) or level-activated
(gated). Programmable polarity (rising/falling edge trigger,
high/low gate).
|
Software-configurable for above/below reference, in/out window and
hysteresis.
Programmable polarity (rising/falling edge trigger, high/low gate).
Trigger levels set by DAC0 and/or DAC1. |
Unlimited
pre- and post-trigger samples. Total number of samples must be <256.
Compatible with both Digital and Analog trigger options. |
|
Digital Input/Output
| Digital Type |
82C55A |
| Configuration |
2 banks of 8, 2 banks
of 4; programmable by bank as input or output |
| Number of channels |
24 I/O |
| Output High |
3.0 volts min @ -2.5mA |
| Output
Low |
0.4 volts max @ 2.5 mA |
| Input High |
2.0 volts min, +5.5
volts absolute max |
| Input Low |
0.8 volts max, -0.5
volts absolute min |
| Power-up / reset state |
Input mode (high
impedance) |
| Interrupts |
INTA# - mapped to IRQn
via PCI BIOS at boot-time |
| Interrupt
enable |
Programmable |
| Interrupt sources |
Residual counter,
End-of-channel-scan, AD-FIFO-not-empty, AD-FIFO-half-full |
|
Counter Section
| Counter type |
82C54 |
| Configuration |
Two 82C54 devices.
three down-counters per 82C54, 16 bits each |
| 82C54A
(Counters #1, 2 & 3): |
Counter 0 - ADC
residual sample counter.
| Source: |
ADC Clock. |
| Gate: |
Internal programmable
source. |
| Output: |
End-of-Aquisition
interrupt. |
Counter 1 - ADC Pacer Lower Divider
| Source: |
10 MHz oscillator |
| Gate: |
Tied to Counter 2
gate, programmable source. |
| Output: |
Chained to Counter 2
Clock. |
Counter 2 - ADC Pacer Upper Divider.
| Source: |
Counter 1 Output. |
| Gate: |
Tied to Counter 1
gate, programmable source. |
| Output: |
ADC Pacer clock (if
software selected), available at user connector (A/D Internal
Pacer Output). |
|
|
82C54B: |
Counter 0 -
Pretrigger Mode: =
| Source: |
ADC Clock. |
| Gate: |
External trigger |
| Output: |
End-of-Acquisition
interrupt. |
Counter 0 - User Counter 4 (when in non-Pretrigger
Mode)
| Source: |
User input at 100pin
connector (CLK4) or internal 10MHz (software selectable) |
| Gate: |
User input at 100pin
connector (GATE4) |
| Output: |
Available at 100pin
connector (OUT4) |
Counter 1 - - User Counter 5
| Source: |
User input at 100pin
connector (CLK5) |
| Gate: |
User input at 100pin
connector (GATE5) |
| Output: |
Available at 100pin
connector (OUT5) |
Counter 2 - User Counter 6
| Source: |
User input at 100pin
connector (CLK6) |
| Gate: |
User input at 100pin
connector (GATE6) |
| Output: |
Available at 100pin
connector (OUT6) |
|
| Clock input frequency |
10 MHz max |
| High pulse width
(clock input) |
10 MHz max |
| High pulse width
(clock input) |
30 ns min |
| Low pulse width (clock
input) |
50 ns min |
| Gate width low |
50 ns min |
| Input low voltage |
0.8V max |
| Input high voltage |
2.0V min |
| Output low voltage |
0.4V max |
| Output high voltage |
3.0V min |
|
Environmental
| Operating Temperature
Range |
0 to 70°C |
| Storage Temperature
Range |
-40 to 100°C |
| Humidity |
0 to 90%
non-condensing |
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| Price: |
| Sale Price: |
| Your Price: |
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| * Contact Embedtec for other configurations and quantity discounts. |
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